Semiconductor devices are manufactured by forming active regions in a semiconductor substrate, depositing various insulating, conductive, and semiconductive layers over the substrate, and patterning them in sequential steps. The upper or last-formed layers of the semiconductor device typically comprise metallization layers. The metallization layers typically comprise one or more layers of metal interconnect having conductive lines disposed within an insulating material and may provide connections to underlying active regions and connections within and over the substrate. The metallization layers comprise low or ultra low dielectric constant materials as insulating material to minimize capacitive coupling between the conductive lines. However, low or ultra low dielectric constant materials have poor mechanical properties and are susceptible to failure, for example, due to delamination.
In conventional package configurations, an IC in the form of a die is secured to a printed circuit board (PCB). After curing, the die is electrically connected to the PCB and encapsulated with a mold compound to form a complete package. During fabrication, tremendous thermal mismatch occurs between all these structures generating intense mechanical stress. For example, low-k or ultra low-k dielectric layers within the metallization layers of the die may be compromised, and may delaminate resulting in chip failure. The presence of through substrate vias magnifies the problem due to an increase in stress around the through substrate vias.
Hence, what is needed in the art are improved structures and methods of forming chips without significantly impacting reliability.